Advancements in semiconductor technology have made possible memory chips with over a million locations for storing bits of data information. While each generation of memory chips at least doubles the number of storage locations, the size of the integrated circuit chips must yet be maintained within certain limits to enhance production yield and accommodate conventional packaging schemes.
A majority of dynamic random access memories (DRAMs) are fabricated using the metal oxide silicon field effect transistor (MOSFET) technology, and therefore the circuits can be reduced in area simply by scaling to a smaller dimension. That is, all dimensions of the various process masks are uniformly shrunk so that the resulting circuitry can be fabricated in a smaller area on the wafer. The scaling of a MOSFET circuit is effective to reduce the wafer area accommodated by a circuit, within certain limits. One limitation in scaling an integrated circuit is the photolithographic techniques used to form and maintain registration of the various masks.
Another limitation which is especially important in fabricating smaller area DRAM cells is that the capacitance of the storage capacitor must be of at least a specified value. With sufficient capacitance, a charge can be stored in the capacitor, and later recovered as a signal of significant magnitude to be detectable over noise and other electrical interference. Also, the capacitance of the storage capacitor must be of such a value so that memory refresh cycle times do not become appreciable in comparison to the normal read and write operations of the memory.
Various approaches have been taken to reduce the cell size of DRAMs without comprising the storage capacity of the capacitor. One approach commonly taken in the art to conserve semiconductor wafer area is to form the capacitor storage element under the surface-fabricated transistor of the cell. This is accomplished by forming a V-groove in the surface of the substrate, forming the cell transistor in the inclined face of the V-groove, and the capacitor thereunder. This type of device is commonly referred to as a V-MOS device. While the V-groove type of device is effective in conserving substrate space, difficulties are encountered in masking and fabricating the irregular contour of the V-groove device.
A problem attendant with the placing of a large number of semiconductor devices in a small area is the erroneous operation thereof due to electron and hole charge generation caused by alpha particles entering the wafer. With a close spacing between adjacent circuits, the electron or hole charge generated in one circuit by an alpha particle can be transferred to an adjacent circuit and create the potential of erroneous operation. When this occurs, the neighboring cells are momentarily connected together, resulting in the possible loss of information. Alpha particle interference is particularly disruptive of operations in logic circuits, and especially in DRAM cells when the small storage capacitors can be quickly discharged by the addition of holes or electrons to the charged capacitor plates.
From the foregoing, it can be seen that a need exists for a dynamic random access memory device which requires very little substrate space, but which does not sacrifice capacitance storage capabilities. A concomitant need exists for a DRAM cell which is more resistant to alpha particle problems, and which can be easily and economically fabricated using current process techniques.